Senior Manager, Verification

Senior Manager, Verification

Hyderabad / Secunderabad
0 - 50 Years
Not Specified

Job Description


Job Description
About this Position:

  • Write verification specifications, verification plans, and documentation
  • Develop test bench and automate regression plans
  • Be responsible for simulations, verifications, and debugging of logic designs (schematics, RTL)
  • Be responsible for developing testbenches , test cases and verification flow components for Soc based FPGA
  • Develop tests with software/firmware flow used in SoC FPGA verification
  • Development of Behavioral models using Verilog and SystemVerilog
  • Develop Coverage driven Verification flows
  • Develop and complete block-level verification and contribute on test development for SoC FPGA fullchip level verification
  • Bring a self-motivated and enthusiastic approach that will achieve any new requirements and

overcome all challenges
  • Able to work independently and handle complex Block and Subsystem Verification platform
  • Able to debug the logic designs for design intent and Interface with cross-functional teams and

collaboration in all verification related activities
Qualifications:BSEE or MSEE
Required Skills and Experience:
  • Hands on project experience in RTL Verification
  • Strong knowledge on digital fundamentals and understanding of FPGA/ custom chip flow
  • Hands on knowledge on Verilog and SystemVerilog
  • Hands on knowledge in C/ C++ language
  • Experience in FPGA programming and related software usage with Firmware handling knowledge is a plus
  • Exposure to SVF and STAPL/JAM: Adaptive FPGA Programming is a plus
  • Good Knowledge in logic design and analysis
  • Experience with UNIX shell scripting or Perl scripting
  • Experience in Verilog, SystemVerilog, UVM
  • Exposure to SoC FPGA flow concepts
  • Exposure to Gate Level Simulations and Firmware Verification
  • Exposure to knowledge on System Verilog Assertions, Functional Coverage and Scoreboard
  • Experience with leading edge simulator tools is recommended
  • Good analytical and problem solving skills
  • Excellent written and verbal communication in English.
  • Willingness to travel on short notices occasionally
Job Requirements
Qualifications:BSEE or MSEE
Required Skills and Experience:
  • Hands on project experience in RTL Verification
  • Strong knowledge on digital fundamentals and understanding of FPGA/ custom chip flow
  • Hands on knowledge on Verilog and SystemVerilog
  • Hands on knowledge in C/ C++ language
  • Experience in FPGA programming and related software usage with Firmware handling knowledge is a plus
  • Exposure to SVF and STAPL/JAM: Adaptive FPGA Programming is a plus
  • Good Knowledge in logic design and analysis
  • Experience with UNIX shell scripting or Perl scripting
  • Experience in Verilog, SystemVerilog, UVM
  • Exposure to SoC FPGA flow concepts
  • Exposure to Gate Level Simulations and Firmware Verification
  • Exposure to knowledge on System Verilog Assertions, Functional Coverage and Scoreboard
  • Experience with leading edge simulator tools is recommended
  • Good analytical and problem solving skills
  • Excellent written and verbal communication in English.
  • Willingness to travel on short notices occasionally

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