R&D Engineer, II

R&D Engineer, II

Synopsys India Private Limited
Noida India
8-11 years
Not Specified

Job Description

The Embedded Memory and Logic Team in Noida is part of Solutions Group and is responsible for standard and custom embedded/ROMs development and provides both functional and physical views of memory in form of Memory compilers, A(IP) for the design of complex. The team is completely responsible for all aspects of memory development starting from Bit Cell Analysis, Architecture Design, Characterization and Verification.
In this role, the Senior Engineer will be part of team contributing to Different type of Architectures of embedded SRAM, Register files and ROM.
As Senior Engineer, the individual will be involved in challenging projects and drive it to completion in record time. You will quickly ramp on the existing flow, understand the challenges, and produce the work plan. Your expertise in deep submicron technology and Finfet,SRAM design,processor design,Digital design flowand teamwork skills will be highly leveraged to guide activity across the entire cross-discipline, multi-site team. You will work with others to identify the issues, get buy-in on proposed solutions, and implement the solutions in time for the team to execute to schedule.
  • Develop Multiport SRAM/Register file architectures and circuit implementation techniques.
  • Schematic entry, simulation of major blocks, layout planning, layout supervision and interface with CAD team for full verification and model generation.
  • Designing and implementing optimum low-power and area-efficient embedded memory (SRAM, register files, etc.) circuits and architectures.
  • Learn and apply skills in memory compilers having Transistor level circuit Design.
  • Resolves a wide range of issues in creative ways
  • Inter-teaminteraction
  • customer focus
  • Frequently networks with senior internal and external personnel in own area of expertise
  • Experience of FinFet Technology for Memory Design
  • Can coordinate, facilitate and monitor the daily activities of a small to large group of support resources within their section or project team
  • While holding a leadership role is able to control to the memory development at a prominent level
  • With minimal supervision, prioritizes workload to successfully manage multiple tasks and responsibilities
  • Proactively addresses and communicates issues impacting productivity

  • BE/B.Tech/ME/M.Tech/MS in Electrical & Electronics Engineering from premium institute/university with minimum of 8 years of experience in VLSI Design
  • Deep understanding of SRAM/Register File architectures and advanced custom circuit implementations.
  • Exposure to full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation.
  • Direct experience with the most advanced technology nodes. Familiarity with variation-aware design in nanometre technology nodes
  • Wmastery in scripting using Perl, python for automation
  • Deep understanding of SRAM single port and multi-port design
  • Floor planning
  • Expertise using leading-edge EDA tools Synopsys, Cadence or Mentor Graphics from a CAD tool perspective, experience with floor planning tools, P&R flows and physical design verification flows is required.
  • Understanding of RC circuit of 1stand 2ndorder.
  • Basics ofDigital design (realizationof Boolean function using Gates, Mux etc)
  • Fundamentals ofTransfer function and its analysis forstability etc.
  • Strong CMOS fundamentals
  • Knowledge of CMOS fabrication
  • Good digital design knowledge
  • Exposure to basic analog fundamentals

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