Principal STA Engineer

Principal STA Engineer

Mulya Consulting
Hyderabad / Secunderabad
12-16 years
Not Specified

Job Description

Principal STA Engineer
Location : Hyderabad

This position is a permanent position with our client (US Based Semiconductor Product Company with revenue more than 30 Billion USD)
Our client is a world leader (Top5 Semicon Company in 2018) in innovative memory solutions that transform how the world uses information. They have over 34,000 team members in 17 countries who work with the world’s most trusted brands, delivering memory and storage systems for a broad range of applications and sparking countless possibilities in technology
our vision is to transform how the world uses information to enrich life and our commitment to people, innovation, tenacity, collaboration, and customer focus allows us to fulfill our mission to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community.
In this role as a Principal STA Engineer in Non-Volatile Engineering Group, you will be responsible for crafting next generation products for using the newest technology. You will also work with design teams across various subject areas in helping developing a robust design practices for predictable and accelerated sign-off
Responsibilities include, but not limited to:
  • Strong STA fundamentals.
  • Drive RTL development to be constraint friendly, measure efficiency & improve constantly
  • Constraint creation/development for SERDES/source synchronous designs
  • Constraint creation/development for functional as well as DFT modes
  • Lead and developed constraints for designs with complex clocking schemes and scenarios
  • Has done PoR creation for timing sign-off including timing margin calculations independently atleast for one project
  • Experience handling STA of multi-power domain designs & constraint mode merging
  • STA flow development, abstraction with bottleneck identification
  • TAT reduction in multi-mode, multi power domain/DVFS designs
  • Interface to design team and PD team and drive TAT reduction for PD.
  • Generate timing ECOs for Physical design
  • Drive ambitious schedules, and enables dependent teams to accomplish
  • Has experience in mentoring junior engineers

Minimum Qualifications:
  • A minimum with 12-16 years of total experience in RTL development/coding, constraint development, full chip STA experience
  • Has done at least one full chip timing sign-off as hands-on lead
  • Must have experience atleast once as sole accountable STA lead for a new device/SoC.
  • Proficient in design margins
  • Proficient in SDC constructs
  • Proficient with EDA tools from Synopsys/Cadence/Mentor
  • Proficient in Tcl and Perl
  • Excellent analytical & communication skills
  • Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone

Preferred Skills:
  • RTL coding/development/micro architecture exposure
  • Strong interpersonal skills both written and verbal
  • You are ambitious, goal-oriented, and committed
  • You enjoy start-up kind of environment

In this role as a Principal STA Engineer in Non-Volatile Engineering Group, you will be responsible for crafting next generation products using the newest technology. You will also work with design teams across various subject areas in helping developing a robust design practices for predictable and accelerated sign-off
Responsibilities include, but not limited to:
  • Strong STA fundamentals.
  • Drive RTL development to be constraint friendly, measure efficiency & improve constantly
  • Constraint creation/development for SERDES/source synchronous designs
  • Constraint creation/development for functional as well as DFT modes
  • Lead and developed constraints for designs with complex clocking schemes and scenarios
  • Has done PoR creation for timing sign-off including timing margin calculations independently atleast for one project
  • Experience handling STA of multi-power domain designs & constraint mode merging
  • STA flow development, abstraction with bottleneck identification
  • TAT reduction in multi-mode, multi power domain/DVFS designs
  • Interface to design team and PD team and drive TAT reduction for PD.
  • Generate timing ECOs for Physical design
  • Drive ambitious schedules, and enables dependent teams to accomplish
  • Has experience in mentoring junior engineers

Minimum Qualifications:
  • A minimum with 12-16 years of total experience in RTL development/coding, constraint development, full chip STA experience
  • Has done at least one full chip timing sign-off as hands-on lead
  • Must have experience atleast once as sole accountable STA lead for a new device/SoC.
  • Proficient in design margins
  • Proficient in SDC constructs
  • Proficient with EDA tools from Synopsys/Cadence/Mentor
  • Proficient in Tcl and Perl
  • Excellent analytical & communication skills
  • Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone

Preferred Skills:

  • RTL coding/development/micro architecture exposure
  • Strong interpersonal skills both written and verbal
  • You are ambitious, goal-oriented, and committed
  • You enjoy start-up kind of environment

About Us
As the leader in innovative memory solutions, we are helping the world make sense of data by delivering technology that is transforming how the world uses information. Through our global brands — Crucial and Ballistix — we offer the industry’s broadest portfolio. We are the only company manufacturing today’s major memory and storage technologies: DRAM, NAND, NOR and 3D XPoint™ memory. Our solutions are purpose built to leverage the value of data to unlock financial insights, accelerate scientific breakthroughs and enhance communication around the world.

This position is a permanent position with our client (US Based Semiconductor Product Company with revenue more than 30 Billion USD) Our client is a world leader (Top5 Semicon Company in 2018) in innovative memory solutions that transform how the world uses information. They have over 34,000 team members in 17 countries who work with the world’s most trusted brands, delivering memory and storage systems for a broad range of applications and sparking countless possibilities in technology  

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