Location : Hyderabad
This is a permanent position with our client (US Based Product MNC with revenue of more than 30 Billion USD) our client is a world leader in innovative memory solutions that transform how the world uses information.
For nearly 40 years, our company has been instrumental to the worlds most significant technology advancements, delivering optimal memory and storage systems for a broad range of applications. Responsibilities include, but not limited to: Hands-on write constraints for designs with complex clock structures Constraint& mode reduction, own design timing across functions Drive Design margins Setup distributed processing flows for STA Generate timing ECOs for Physical design Validate timing constraints Build/Create PoR for STA Come up with innovative ways to reduce TAT and bring more predictability.
Mentor junior engineers Minimum Qualifications:A minimum with 8-16 years of physical design experience Has done atleast one full hands-on TO in 16nm or below.
Proficient in design margins Proficient in SDC constructs Proficient with EDA tools from Synopsys/Cadence Proficient in Tcl and Perl Excellent analytical skills Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone Preferred Skills:Strong interpersonal skills both written and verbal You are ambitious, goal-oriented, and dedicated Collaborate effectively in a dynamic environment
Mining the knowledge Community
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