As a member of Microchip’s engineering community, your primary responsibility will be to design, simulate, and verify the ESD solution for an advanced FPGA. The FPGA is a System On Chip containing multiple power supplies, ASIC logic blocks, custom circuit blocks, and three types of high speed, programmable IO buffers. As a secondary assignment, you will contribute to the development of high speed programmable FPGA IO used in DDR4 memory interfaces.
Duties & Responsibilities
- Develop overall ESD plan for high speed SERDES; high speed DDR Memory IO buffer; flexible 3.3V to 1.1V General purpose IO buffers, and multiple core and auxiliary power supplies.
- Simulate and confirm all critical operating parameters, e.g. Vbreakdown, Ron, Von, etc., for ESD components supplied by Foundry.
- Propose and develop custom clamps or other ESD components. Plan and include ESD circuits on test shuttles. Plan for testing of the shuttle silicon. Incorporate results and components into ESD plan.
- Propose and drive to closure ESD specs and targets.
- Develop ESD schematics and simulate discharge paths for all ESD diode/clamp structures.
- Develop 3.3V power clamp.
- Define ESD layout metallization rules, help guide DRC rule decks for ESD and latchup checking.
- Work closely with layout team on ESD integration at block and full chip level as well as run Pathfinder, or equivalent, to verify metal resistances in ESD discharge paths.
- Work closely with 3rd party SERDES vendor to define the optimal ESD solution achieving minimum pad cap, implement Tcoil in SERDES for capacitance isolation, and optimal signal integrity.
- Optimize driver structures for parallel ESD discharge through driver parasitic paths.
- Creation of a detailed ESD Design Review document for the first product.
- Support derivative devices and package options by re-running Pathfinder.
- Work with 3rd party ESD supplier or testing facility as required.
IO Buffer Design and Development –
- This is a secondary job function with ESD being primary. Entails some or all the following:
- Design and develop high speed FPGA IO buffer operating from 1.8V down to 0.5V including:
- PVT compensated output driver with pre-emphasis function.
- High speed single ended and differential receiver including CTLE/equalization.
- High speed voltage translators.
- Near/far end parallel LVDS termination; DDR memory single ended ODT termination.
- Programmable for drive strength, mode, output voltage, input ODT termination value.
- Write specification. Provide Datasheet specifications.
- Simulate AC paths and perform functional verification.
- Create detailed Design Review document.
- Support verification staff and timing characterization team.
- Minimum of several successful previous ESD developments.
- High degree of SPICE simulation proficiency.
- Demonstrated competency in scripting, managing simulation queues, and data capture plus presentation using Microsoft Office tools, including Excel.
- Ability to support layout, verification, or timing characterization.
- Ability to evaluate ESD clamps and diodes for latchup and other radiation hazards.
- Ability to run Pathfinder, interpret results and resolve issues with layout team.
- Cadence Composer schematic entry. Full custom design tool set.
- Good analytical, oral and written communication skills
- Able to write clean, readable presentations.
- Self-motivated, proactive team player.
- Ability to work to schedule requirements.
- Analog and full custom design experience.
- Experience in FPGA or ASIC development and full chip integration.
- ESD test, TLP test.