We're a strong, vibrant cross-site team who define, create and develop the environment and test suites that we use to validate Network Accelerators products, AI, Security Accelerators, Storage Accelerators, Edge compute SOCs, at the IP and Full chip level and working on cutting edge of AI, compute, networking, memory product using latest CPU/Custom Cores/Bus architectures.
As part of this team you will help build a team that will work collaboratively with our peer SV teams, RTL hardware design, verification, software engineers, and platform teams to define and implement requirements for post silicon validation throughout the product life cycle.
You will be embedded within the mentioned teams to work in collaboration towards common test strategies and execution of those plans.
We need your skills and talent in system validation to apply smart debug techniques to characterize Full Chip functional flows and issues as well as test feature correctness/performance to specifications and use cases validation both in the pre-silicon and post-silicon space for Network SOC/ASIC.
Area's such as Inter IP Full Chip validation verifying Ethernet network and virtualization, Power Management, Debug/DFX, Clocking, Reset, interrupts and Security.
As a successful system validation technical lead on our team, you'll be responsible for leading and developing the methodologies we use, executing validation test plans, and debugging failures that we find in Full Chip and Networking IPs/products.
We'll need you to have a broad understanding of multiple areas of computer architecture and system design, technical test content development, and you'll be required to interface with our peers in SW, Architecture, Silicon Design, and Pre-silicon Verification. We'll also need you to continue to improve our test content and provide feedback for the design and evolution of our future on-die debug and validation features.Required Qualifications:
• Master's degree in Electrical Engineering, Computer Engineering or Computer Science with 4-15 years of relevant industry experience.
• Solid understanding of the PCIe protocol and the validation of PCIe interfaces or any high speed IO.
• Hardware and/or software development/debugging skills
• Direct Post-Silicon validation experience
• Experience with clocking / resets
• Experience with DFX (JTAG, Array freeze and dump)
• Experience with lab equipment (Logic Analyzer, Oscilloscope, thermal streams, protocol analyzers)
• Experience with C, Perl and/or Python
• Experience in developing test plans
• Object Oriented programming skills.
• Experience developing test automation.