Physical Design Manager

Physical Design Manager

Sign On Solutions Private Limited
15-20 years
Not Specified

Job Description

Position Description/Responsibilities:
We are looking for a dynamic and hands on Technical Project Manager who can actively contribute, coach, mentor and leads the team members to deliver projects in Physical Design (Place and Route) of Digital and Mixed Signal Block/Full-Chip Designs. The manager will proactively communicate and integrate local and remote physical design teams seamlessly and works with peers in other technical teams, Clients and Customers. The manager will actively drive development/enhancement of Physical Design Methodologies. The main responsibilities include Creating Project Schedule, Estimate required resources (EDA Tools/Licenses, Engineering Skillset, Computing Resources), Track the project progress against schedule, Predict the risks ahead of time, Manage Deliverables Ontime with Assured Quality, Support the project post Delivery/Tapeout including post Silicon debug. Further the manager will also manage building the teams grounds up by Mentoring, Training Juniors/Freshers and ramping them up on projects.

Job Requirements / Skillset Required:
* BE/BTech in ECE or MTech/MS in Digital Electronics/VLSI
* Experience (15+ Years) in Physical Design, Should have managed at least 5+ Chip Tape-outs
* EDA Tools - Good command on Synopsys’s ICC/ICC2, PrimeTime, Cadence’s – Innovus/Tempus, Mentor’s Calibre-LVS/DRC
* Experience in multimillion gate designs in 7um, 10nm, 14um, 16um 28nm and 45nm TSMC/Samsung/Intel/GF technology nodes
* Logic Synthesis, Timing Constraints debug and development
* Low Power Designs – Voltage Islands, Power Gating Implementation
* Floor Planning, Power Planning, Place and Route at block level and chip level
* Auto CTS methodology for complex clock trees and Debugging to achieve best Insertion Delay/Clock Skews
* Full/Semi Custom Clock Tree Implementation
* Strong Debugging skills in resolving Congestion and Timing, SI/CrossTalk Analysis and Write Timing/Functional ECOs.
* Debug Failures in Formal/Functional Verification
* Chip/IP Integration (Custom/Semi-Custom and Auto-PnR Physical Blocks)
* Tape out signs off checks (PnR, RC-Extraction, STA, LVS, DRC, DFM, ESD, IR, Signal/Clock/Power-EM)
* Strong in Physical Verification (DRC/LVS)
* Good at scripting in TCL, PERL, Shell etc
* Excellent Verbal/Written communication skills
Good to have:
* DFT (JTAG, BSCAN, MBIST), DFT Insertion and DFT Verification
* Exposure to Analog Circuit design and Custom layout design

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