Physical Design Engineer

Physical Design Engineer

4-7 years
Not Specified

Job Description

Job Description
In this role you will be part of Intel's Barefoot Divisions physical design team working on innovative programmable switch ASIC roadmap. You will engage with Architecture, DFT and packaging to arrive at optimal chip planning early in the design cycle. You will be part of our physical design team working closely with cluster and partition leads to comprehend design challenges and arrive at optimal floorplans. You will play a critical role in die estimation and in evaluating floorplan tools, methods and flows. Your work will involve meticulous planning of various aspects of floor planning for optimal data flow for high pin densities and to facilitate high confidence timing closure and routability. With your broad understanding of physical design, you will play a critical role in identifying and solving multitude of design issues at partition/cluster and full chip.
Minimum Qualifications BS in Electrical or Computer Engineering or similar degree with 4+ years of experience or MS in EE with 2+ years 3+ years in physical design and experience on block closure 2+ years with hands on synthesis and APR expertise using DC/Genus/ICC/FC/Innovus. 2+ years of experience in floor planning and global timing verification and Physical Design Verification Flows 2+ years of experience in floor planning tools such as ICC2 DP or Cadence Innovus. 2+ years of experience with SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration Preferred Qualifications 2+ years of experience Hierarchical design approach, top-down design, budgeting, timing and physical convergence 2+ years of experience Integrating IP from both internal and external vendors and to specify and drive IP requirements in the physical domain 2+ years of Experience with large SoC designs with power/performance upwards of 1GHz and die challenges. 1+ years of experience in various process related design issues including Design for Yield and Manufacturability, multi Vt strategies.Inside this Business Group
The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.
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