Physical Design Engineer

Physical Design Engineer

Intel
Not Specified
Not Specified

Job Description


Job Description :
Job Description
Creates bottomsup elements of chip design including but not limited to FET, cell, and blocklevel custom layouts, FUBlevel floor plans, abstract view generation, RC extraction and schematictolayout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, autoplace and route algorithms, floor planning, fullchip assembly, packaging, and verification. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires expansive knowledge and practical application of methodologies and physical design.
Qualifications
BE, with 3-6 Yrs of Experience doing Analog IPs like Serdes, PLL, PCIe, Display Port, DDR, USB. Handles block layout independently ensuring quality schedule of deliverables No supervision by lead Works with lead on full chip layout floor plan power grid templates etcGood understanding of RV ESD RoutingKnows all flows and tools like Virtuoso, ICV, Calibre, Redhawk, Totem, Extraction tools.Works with DE to identify tasks does planning and scheduling of the deliverablesInside this Business Group
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.
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About Intel

Job Source : jobs.intel.com

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