Physical design engineer

Physical design engineer

Intel
Not Specified
Not Specified

Job Description


Job Description :
Job Description
Charter of the CLE-India CFE team in Programmable solutions group is to do SoC's for its line of products.
Seeking an individual who has technical expertise in the RTL to GDSII Implementation of the ASIC design flow
The position calls for execution/implementation of projects either at Sub-system level and/or SoC level
The role requires interaction with various SoC team like FE/RTL/DFT/PD/STA team, Flow/Methodology team and other teams working on the SoC/Product
Working with tool/flow owners and vendors for ongoing tool/methodology improvement with an objective to meet the SoC/Product specs
The responsibilities will focus on the RTL to GDS flow and may include but not be limited to
SDC/Constraint understanding, generation, clock and timing closure
Synthesis with Synopsys Design Compiler DCT or industry equivalent
Low Power Domain Analysis using standard Power Formats UPF/CPF
Place and Route and clock tree synthesis with Synopsys ICC2 or equivalent tools
Static Timing Analysis with Synopsys Primetime or equivalent tools
Formal equivalence checks
Layout Verification and DRC analysis
Static/Dynamic IR analysis
The ideal candidate should exhibit the following behavioral traits
Strong verbal and written communication skills
Strong initiative and analysis/problem solving skills
Able to work in a diverse team environment and with remote teams
Motivation and drive to continuously push design convergence and productivity
Qualifications
Qualification:
A Bachelor or Masters of Engineering degree in Electrical/ Electronic/VLSI Engineering or related field
4 or more years of ASIC/SoC/Chip design industry experience of implementation at IP/Sub-system and SoC's level
The role requires good hands-on experience in many technical areas like floorplanning, APR, STA, FEV, UPF, Low Power designs, IR/EM analysis and DRC/LVS
Good understanding of timing convergence process and proven track record in resolving physical design issue like placement, congestion, CTS, routing
Should be able to corelate timing closure issues with place and route tools
Conversant with low power designs implementation
Hands on with EDA industry standard place and route tools from Synopsys and Cadence
Perl/TCL or any scripting language knowledgeInside this Business Group
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.
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