Lead Design Engineer

Lead Design Engineer

Cadence Design Systems (India) Pvt Ltd
Not Specified
Not Specified

Job Description

Job Description :
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description:
  • Hand-on work experience in ASIC/IP/Subsystem/SOC/PHY level Verification primarily in protocols PCIe / NVMe / USB /SATA
  • Extensive experience in developing Verification environment and methodologies using Verilog / System Verilog / UVM / OVM / 'e' Specman based languages
  • Proficient in PCIe PHY based protocol checkers / assertions using Verilog / SVA
  • Knowledgeable in integrating Serial-link VIPs, Verilog Real modelling of analog behavior and debug in various Industry Simulation tools
  • Hands on in regression setup, Coverage / Metric analysis and Vplan are preferable
We're doing work that matters. Help us solve what others can't.

Job Details

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. 
Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

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