Urgent Opening for Sr. Manager - PDD (Product Design & Development , R & D) for Nashik location.
We are hiring for a candidate who has Railway Sales and Marketing experience for CLW/DLW/ICF etc. for Mechanical items who is presently working at a Senior Level
• Write verification specifications, verification plans, and documentation • Develop test bench and automate regression plans • Be responsible for simulations, verifications, and debugging of logic designs (schematics, RTL)
Builds company image by collaborating with customers, government, community organizations, and employees; enforcing ethical business practices. Maintains quality service by establishing and enforcing organization standards.
Ability to handle governance bodies Strong Analytic Skills Strong Decision Making Skills Leadership Skills Proven managerial skills for leading a team Excellent Interpersonal and leadership skills Ability to communicate confidently and
Excellent Communication, Writing, Problem Solving, Scheduling and ability to work well under intense pressure. Build strategic relationship and partner with key industry players, agencies and vendors. Required Minimum Graduate and above.
The successful candidate will work to become familiar with SOC/FPGA product line and provide customer focus solutions, application designs and design services in the area of High Speed protocols and Video Imaging Solutions.
• Define and develop verification architecture and verification plan • Define and develop verification methodologies • Define and develop verification environments • Write verification specifications, verification plans, and documentation
Work with multiple project teams internal and outsourced development partners responsible for all stages of quality assurance for complex products and platforms, including testing strategy, analysis, coding, results evaluation, and proposed correct
Develop and execute implementation plans to synthesize, implement Design For Test, and close timing on complex digital integrated circuits at the block, subsystem or chip level, which are coded in VHDL/Verilog.
Define and develop verification architecture • Define and develop verification methodologies • Define and develop verification environments • Write verification specifications, verification plans, and documentation
• Setting up the verification methodology, EDA environment, design flow, for SoCs with embedded analog processor cores & IPs, from RTL to post physical design verification • Delivery of fully verified – including both functionally and test coverage w
Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO generation at top level, handshaking with blocks for timing/functional ECO implementation, good exposure in Synthesis for block and top level.