FPGA/RTL Design Engineer

FPGA/RTL Design Engineer

Company Name Confidential
3-12 years
Not Specified

Job Description

• Minimum 2+years of experience in FPGA/RTL Design
• Experience in Verilog or VHDL Coding,
• Good knowledge on Digital Design concepts, ,Should have good experience in RTL coding,
• Hands on experience on FPGA tools flow (Xilinx, Altera etc.)
• should have experience in Xilinx FPGA, Zynq.
Should have good experience in Timing Analysis, FPGA PNR for high speed designs, using FPGA hard macros, experience with Xilinx 5G building blocks
Able to guide and lead team of 3-4 members.
Good in debugging skills

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