Formal Verification Engineer

Formal Verification Engineer

Intel
Not Specified
Not Specified

Job Description


Job Description :
Job Description
Develops and applies computer aided design CAD software engineering methods theories and research techniques in the investigation and solution of technical problems Assessing architecture and hardware limitations plans technical projects in the design and development of CAD software Defines and selects new approaches and implementation of CAD software engineering applications and design specifications and parameters Develops routines and utility programs Prepares design specifications analysis and recommendations for presentation and approval May specify materials equipment and supplies required for completion of projects and may evaluate vendor capabilities to provide required products or services
Qualifications
Engineers should possess a Masters degree in Computer Science Electrical Engineering Mathematics Specialization in formal verification is preferableDesignVal engineers who want to try the new paradigm in verification are welcome to apply Formal Verification being a sought after capability can help the engineer get a fresh perspective on proving a designInside this Business Group
The Design Engineering Group is a worldwide team responsible for the design, development, validation, and manufacturing of IPs and SOCs. Our mission is to deliver leadership products through groundbreaking innovations.
Other Locations
Malaysia, Penang
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