ASIC Digital Verification Engineer

ASIC Digital Verification Engineer

Synopsys India Private Limited
Bengaluru / Bangalore India
7-10 years
Not Specified

Job Description

  • This is a verification focused individual contributor’s role.
  • The candidate will be part of the DesignWare IP Verification R&D team at our Bangalore Design Center, India.
  • Specify, design/architect and implement state-of-the-art Verification environments for the DesignWare family of synthesizable cores and perform Verification tasks for the IP cores.
  • Work closely with RTL design team and be part of a global team of expert Verification Engineers.
  • Domains will include but not be limited to USB, PCI Express, Ethernet, AMBA.
  • Job role will have a combination of Test Environment Architecture planning, Test planning, Leading implementation of test environment, Test cases & FC. Leading team to meet quality metric goals and regression management.

  • BS/BE in EE with 7+ years of relevant experience or MS with 6+ years of relevant experience in the verification of IP cores and/or SOC verification.
  • Experience in architecting & developing HVL based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage.
  • Strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and relevant debugging tools.
  • Exposure to verification methodologies such as UVM/VMM is required.
  • Familiarity with HDLs such as Verilog and scripting languages such as perl is required.
  • Exposure to IP design and verification processes is required.
  • There will be strong focus on functional & Code coverage driven methodology. So the corresponding mindset is a must.
  • It is essential that the individual has good written and oral communication skills and is able to demonstrate good analysis, debug and problem solving skills and be self-driven
  • Experience in leading team to achieving verification metrics is desired.

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