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STA/Synthesis Engineer / 2 - 4 Years / Hyderabad,Bangalore

Keywords / Skills : Synthesis, DC-topo, RTL, STA

2 - 4 years
Posted: 2018-01-09

Manufacturing/ Engineering/ R&D
Electrical Engineer
Posted On
9th Jan 2018
Job Description

We have multiple positions open for STA & SYNTHESIS Engineer for Hydrabad location.

Fulltime position candidates who join us are required to work at our client place.

Candidate should be very strong in Synthesis & Timing concepts .

Should have knowledge of DC-topo, RTL Compiler or talus.

Should have handled both block and top level.

Should have done both pre and post layout STA.

Synthesis of Block and Top level and the Equivalence checks.

Develop floor-planning and CTS guidelines for layout.

Candidate must analyze pre-layout and post-layout timing, generate Timing and Power.

ECOs, work closely with layout engineers to achieve full chip timing closure.

Must perform in-house quality check before P&R and after P&R.

Power domain checks for Block and Top, CLP.

Candidate will be responsible for RTL integration of various SoC designs, perform various Lint checks to make sure coding guidelines are met for proper synthesizable RTL, compatible for DFT and Low Power.

They will be also involved in the timing constraint development, synthesis and DFT of sub-systems, logic equivalency checks, static low power checks for isolation and level shifter implementations.

Candidate will be responsible for reviews related to timing constraints, synthesis results, DFT coverage results with the team.

You will provide feedback to designers of any DFT, synthesis, low power, and timing issues that need to be addressed.

Desired Candidate

Core Responsibilities:As an ASIC STA Engineer, Candidate will have responsibilities spanning all aspects of SoC design.

Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis and physical implementation)

Must develop and maintain methodology and flows related to timing verification and closure.

Generation of block and full chip timing constraints

Candidate should Be Very Strong In Synthesis & Timing Concepts.should Have Knowledge Of Dc-topo, Rtl Compiler Or Talus.should Have Handled Both Block And Top Level.should Have Done Both Pre And Post Layout STA.
Key Skill(s)

About Company

Morgenall Management Consultant Pvt Ltd
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