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Senior Verification Engineer System Verilog, OVM / UVM -Bangalore and Onsite

Keywords / Skills : Senior Verification Engineer System Verilog, OVM / UVM -Bangalore and Onsite

3 - 12 years
Posted: 2019-04-29

Industry
Recruitment/Staffing/RPO
Function
IT
Posted On
29th Apr 2019
Job Ref code
24
Job Description
Job Description :
Senior Verification Engineer System Verilog, OVM / UVM Skillset Must Have Block and Top level verification know-how Verification Plan Development System Verilog/OVM or UVM Testbench Development VHDL/Verilog simulation and debug Scripting Nice to have HVL: Specman is a plus End to End RTL Functional Verification Concepts Understanding of power aware architecture Experience Must have 3 12 Years Of Experience Performing feature extraction from a specification Coverage closure Experience of other HVLs (e.g. System Verilog) and methodologies (e.g. UVM) Nice to have Experience in Mobility, NFC or Multimedia Applications Job Description Responsibilities Develop Verification Plan and Verification Architecture Develop Tests and Testbench Implement Functional Coverage Points Achieve 100% Functional Coverage Develop Verification Plan Documentation and Capture Results of Execution Location: Bangalore Notice Period: Immediate Joining

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