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Senior RTL Engineers

Keywords / Skills : RTL, Verilog, SOC, ASIC, VHDL, Front End Design, FPGA, Linting, CDC, STA

3 - 11 years
Posted: 2018-10-18

Industry
Semiconductor
Function
IT
Role
Hardware Design Engineer
Hardware Design Technical Leader
Education
BE
BTech
ME
MTech
MS
Posted On
18th Oct 2018
Job Description
Location : Bangalore / Ahmedabad

Our client is a preferred semiconductor design service partners to multiple Fortune 500 companies in the Automotive, Consumer Electronics, Industrial IoT and Medical electronics space. The company enables its customers achieve their time-to-market window by delivering first pass silicon designs and engage with product engineering teams across the globe to designSoC. HQ in, California, with multiple development and services centers in India, Canada , Malaysia and Germany

Practice

RTL Design practice is responsible for that part of the ASIC design flow from Specification/Requirements to RTL. The primary offering of this practice includes Architecture definition, IP/Sub-system Design, SoC Integration, Test chip Design. This practice also does Digital design for Analog that includes Digital controllers for PHYs and works on Analog on Top designs. RTL Design team also has FPGA design capabilities including ASIC conversion and FPGA prototyping using Xilinx/Actel FPGAs. The team ensures quality RTL reducing the iterations of verification and physical implementation thereby enabling lesser time to market.

Qualification/Experience/Skills Required

Hands-on in Verilog/VHDL
Hands on in Linting, Clock Domain Crossing (CDC) checks, equivalence checks
Experience in Digital module micro-architecture and design
Experience in basic RTL simulation
Good knowledge of Synthesis, STA and DFT aware design
Hands-on in Perl/Unix scripting
Hands on in SoC level RTL integration
Excellent analytical, and problem solving skills
Self-motivated, assertive, positive attitude, excellent communication skills and ability to excel in a team environment.
Be able to work with teams at remote locations with different time zone.
Be motivated to continuously develop skills and accept a variety of responsibilities as part of contributing to the project's success
Roles & Responsibilities

Perform Microarchitecture and detailed block design from system requirements/specifications
Perform RTL coding, Lint checks, CDC checks, SDC creation, equivalency checking, STA result review, RTL/gate level simulations debugging
Creating timing constraint file
Working closely with synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power and area goals
Technical interaction with customers and support team
Guiding a team of junior engineers

Job Location: Bangalore, Ahmedabad

Contact:

Uday Bhaskar
Mulya Technologies
"Mining the Knowledge Community"
muday_bhaskar@ yahoo.com

About Company

Our client is a preferred semiconductor design service partners to multiple Fortune 500 companies in the Automotive, Consumer Electronics, Industrial IoT and Medical electronics space. The company enables its customers achieve their time-to-market window by delivering first pass silicon designs and engage with product engineering teams across the globe to designSoC. HQ in, California, with multiple development and services centers in India, Canada , Malaysia and Germany
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