The successful candidate shall work on System Verilog RTL verification related to the
development of power-efficient mobile graphic processors. Specifically we are seeking
someone to integrate and test a number of intricate sub-blocks in the programmable shader subsystem of a low-power Graphics Processing Unit. As this engineer, you will work closely with the implementation and micro-architecture teams and:
Contribute to reviewing with respect to verification the micro-architecture specifications of the shader subsystem Graphic Processor blocks by close interaction with implementation and micro-architecture engineers.
Generate high quality test-bench infrastructures, which are well-documented, extensible and easily invoked by the implementation team.
Assist with the bring-up of complex interactions among the various shader sub-blocks.
Assist the power and performance teams in both measuring the design’s QoR and also in working to verify these metrics.
Debug, repair, and verify logic issues and bugs (both in RTL and gate-level netlists)
Develop a comprehensive test suite for regressions and monitor the results of these tests to ensure regressions are spotted as early as possible.Skill Set:
Desired Skills and Experience
Programming skills using scripting languages (Perl, Python, or other), and C˼++,
Good understanding of RTL verification flow and environments ʎ.g., UVM/OVM, hardware modeling, assertions and formal/semi-formal verification),
High-level Verilog / System Verilog coding skills to allow understanding of the RTL design(s) under test,
Good written/verbal communication skills, strong team work mentality, Motivated, self-directed and able to work effectively, both independently and in a team.
Optional Requirements ("ldquowould like to have"rdquo characteristics)
1. Background in computer graphics with familiarity with overall graphics pipelines,
2. Microarchitecture design experience of GPU or CPU blocks within a relevant sub-system
(Shader core, Texture unit, Memory system, Load/Store, etc.),
3. Familiarity using Synopsys and/or Cadence synthesis tools.