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RTL frontend design Engineer

Keywords / Skills : RTL frontend , design Engineer, Verilog, System Verilog RTL design , RTL synthesis, Design compiler FPGA Flow , Xilinx DFT, MBIST, BSCAN , SCAN , USB2, USB3, Ethernet, SPI, I2c, AHB, APB, 8051/ARM, UPF

6 - 8 years
Posted: 2019-10-31

Industry
Recruitment/Staffing/RPO
Function
IT
Posted On
31st Oct 2019
Job Ref code
27
Job Description
Job Description :
RTL frontend design Engineer RTL frontend design Engineer 6 - 8 years experience in Verilog/System Verilog RTL design and verification RTL synthesis using Design compiler FPGA Flow using Xilinx DFT knowledge of controlling the clock and reset at the RTL level required Knowledge of MBIST,BSCAN , SCAN would be good Ability to work as a team across the geographical location Knowledge of USB2 and USB3 , Ethernet would be added advantage Knowledge of SPI,I2c,AHB,APB,8051/ARM is preferable Knowledge of UPF is required Requirements This Position is based out in Chennai.

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