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Keywords / Skills : RTL Design, RTL Coding, Asic Design, CDC, Linting, FPGA Design, Modelsim, VCS Prime Time, ADC , UPF, System verilog assertion

3 - 13 years
Posted: 2018-11-24

IT/ Computers - Hardware
Hardware Design Engineer
Posted On
24th Nov 2018
Job Description
: Must have 3 to 15 years of practical experience with details of RTL development (VHDL and/or Verilog) including: functional and structural RTL design, design partitioning, simulation and regression, collaboration with design verification team. Must have good familiarity with latest RTL languages and tools, including: simulation systems (e.g. Modelsim, VCS), synthesis tools (e.g. Design Compile), static timing tools (e.g. Prime Time), Linting tools, CDC tools, UPF, code coverage, System Verilog Assertion, etc. Experience with the following area is highly desirable: Strong processor architecture knowledge Microarchitecture implementation Microprocessor integration Low power design Excellent verbal and written communication skills. Ability to work in a team environment. Good self-direction and time management skills

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Stress Consulting
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