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Principal Design Engineer- Bangalore

Keywords / Skills : Design Engineer, RTL Integration , 32 bit microcontroller, RTL, regression simulations, Verilog, System Verilog , SoC integration, RTL verification, Synthesis, CVS/DesignSync , MicroSpyglass, Questa CDC, Modelsim, Design compiler, controller, IC design

6 - 10 years
Posted: 2019-10-31

Posted On
31st Oct 2019
Job Ref code
Job Description
Job Description :
Principal Design Engineer Description SoC level RTL Integration of 32 bit microcontroller product Technical support to the SoC team on integration and System level verification issues Maintaining CVS database for the project Running system level RTL and Gate level regression simulations Providing necessary technical information and technical support to Synthesis, Backend, Test and application teams Requirements Ideal range of experience for this position will be 6 to 10 years. Strong in Verilog/System Verilog HDL Exposure to SoC integration Hands on experience in system level RTL verification, gate level simulations Hands on experience in Synthesis/Timing closure Good in CVS/DesignSync based project database management Exposure to Microcontroller based project development is a plus Exposure on complete IC design development cycle is a plus Knowledge on eesi/CPU/Interrupt controller is a plus Experience of leading small projects is a strong plus Knowledge of EDA Tools- Spyglass, Questa CDC, Modelsim, Design compiler, Primetime etc Soft skills like- team work, Mentoring abilities, presentation skills, Communication skills, Hardworking etc are essential.

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