JD for Physical Design:
Experience: 2.8+ years
Candidate will be responsible for executing the block level place and route assignments from Netlist through GDS flow.
The candidate will own the complete Physical Design including Floor Planning, Power Planning, Place and Route, CTS, Timing Closure, IR Drop Analysis, Physical Verification and Equivalence Checking.
Good understanding of timing, clock tree, routing, and DRC/LVS issues/solutions in complex ASIC designs is required.
Ability to plan and work independently and co-ordinate with cross-functional teams is essential.
Prior experience with 28nm or lower technology nodes is desired.
An expertise in physical verification is desired. The job would require scripting in TCL.
Technologies Tools: -
Netlist to GDSII / PD / Implementation flow / PnR / APR
RTL to GDSII (Synthesis and PD experience)
Low power design experience
ASIC/VLSI flow knowledge.
Floor planning, Power planning, Placement, CTS, Routing, Extraction, DFM
Congestion and timing analysis.
Coming with better QoR
Sign-off flow: STA, DRC/LVS/Antenna/ERC, Power analysis, IR/EM analysis, LEC, ECO (Timing and Functional)
Technology node: 7nm, 10nm, 14nm, 20nm, 28nm, 45nm, 65nm, 90nm,130nm, 180nm (Going forward you can see tech nodes < 7nm)
Scripting skills: Perl, TCL
Qualification: B.E/B.Tech or M.E/M.Tech/M.S in Electrical or Electronics
7338455551 [HIDDEN TEXT]
Salary: Not Disclosed by Recruiter
Industry: Semiconductors / Electronics
Functional Area: IT Software - Embedded, EDA, VLSI, ASIC, Chip Design
Role Category: Programming & Design
Role: Software Developer
Employment Type: Permanent Job, Full Time
PNRTiming ClosurePhysical DesignSTADRCFloor PlanningPhysical VerificationLVSTiming AnalysisPlacement