Leads- Physical Design
Location : Bangalore
No of Positions : 3
Experience : 6-13 years
Own project specific flow setup and maintenance.
Physical design tasks include floor-planning, place and route, CTS, timing closure, IR analysis and LEC for block level, full chip flat and hierarchical designs. Co-ordinate the full chip physical design and verification activities.
Physical design verification tasks include creating setup and scripts for DRC, LVS, Antenna and density checks, report generation, analysis, debug and implementing the fixes in the physical design database. This also includes DFM checks for the advanced node designs.
Ensure correct IP and pad-ring integration in block and flat designs.
Prepare training plan and conduct training of new PD/PDV team members, new tools flow set-up and any tool evaluations.
Work on IDP of the team members, performance management, etc. Responsible for the technical issues in projects running with the team members and guide them to resolve the issues.
Flag PD/PDV flow related issues to relevant person.
Ensure Check list items are followed / Verified within projects.
Take measures which saves time in future projects.( action items in flow revision)
Participate in Focal process
"Mining the knowledge Community"
Email: muday_bhaskar@ yahoo.com
Desired Skills and Experience
Physical Design Physical Verification Static Timing Analysis Timing Closure Floorplanning Clock Tree Synthesis Application-Specific Integrated Circuits (ASIC) Design Rule Checking (DRC) Layout Versus Schematic (LVS) TCL Very-Large-Scale Integration (VLSI) System on a Chip (SoC) STA, DFT, ICC, "first Encounter", "SoC Encounter"