Job Description :
Requirements Must have experience with multiple successful tapeouts for 65nm and smaller geometries. The candidate needs to be self-motivated and an excellent team player, experienced in working with remote teams. Responsible for and own all aspects of physical design (Floorplan, power plan, CTS, Timing closure, Routing) and physical verification efforts at block level and full chip level for flat designs. Hierarchical design experience is desirable. As required - develop, support and maintain physical design flows and methodologies. Candidate needs to have a good understanding of static timing analysis (STA) and sign-off flows Strong hands-on experience with floorplanning, place & route, power and clock distribution, timing analysis and closure with signal integrity, EM/IR and physical design verification activities. Expertise in design tools like Synopsys ICC, DC, PTSI, Formality, StarRC-XT, Mentor Calibre, and Ansys RedHawk. Good software and scripting skills (perl, python, tcl). 8+ years of relevant industry experience in physical design implementation.