• Implementation of physical design for high end server class processor chips in finfet process.
• Responsible to meet block goals for timing, area, and design rules, and will own multiple design blocks from initial RTL to tape out.
• Leading and mentoring junior employees and interfacing with front end design team to improve RTL and design quality.
• Experience performing place and route in finfet process
• Good understanding of concepts of timing and timing closure, cell-based place and route, clocking, fundamentals of logic design
• Expert in developing flows to drive block PnR, Timing Closure and Final sign off.
• Proficiency using Perl/Python, TCL, Make scripting.
• Prior experience with power/clk distribution and analysis, RC extraction and correlation, xtalk analysis, DRC/LVS and tapeout issues.
• Working knowledge of finfet issues.
• Experience with double pattern finfet required, experience with triple pattern process nodes a plus.
• Demonstrates good analysis and problem-solving skills.
• Inherent sense of urgency and accountability.
• Ability to define problems, issues and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.
• Ability to multi-task in a fast paced environment.
• MSEE 8+ years’ experience or BSEE with 10+ years related experience