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Keywords / Skills : Physical Design, Floor Planning, Timing Analysis, Placement and Rout, DRC, LVS, CTS, 7nm, 10nm, 14nm, 28nm, 16nm, 90nm

3 - 13 years
Posted: 2018-12-31

IT/Computers - Hardware
Hardware Design Engineer
Posted On
31st Dec 2018
Job Description
Hands on experience on the entire PD Flow from Netlist to GDSII(Floorplanning, Power Planning, Placement & Optimization, CTS, Routing, ECO, STA)

Working knowledge about OCV, MM/MC optimization and multi power designs (Level shifters, Isolation cells etc)

Exposure STA in designs that have Crosstalk delay OR noise /EM

Strong in areas on CTS and skew fixing

Library preparation in any environment (Synopsys, Cadence etc)

Working knowledge on Physical verifications tasks at lower nodes (data base merging /DRC/LVS/ ERC/PERC/ Antenna/ESD/LUP analysis/fixing ) at block level/chip level

Job would require complete ownership from netlist to GDS for blocks at Block level OR full chip level

Exposure to IP Hardening for blocks like SERDES, USB PHY, MIPI, SATA will be an added advantage

About Company

STRESS Consulting
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