Physical Design Engineer
As part of the MCU32 Design group, the successful candidate will be responsible for Physical Design of 32-bit controllers. The role will include full Chip / SOC integration
from project planning to execution of Netlist-to-GDSII and will be required to drive and enhance Physical design methodologies. It will require a proactive candidate with
a proven record of success in cross functional and cross site team environment .
Qualified applicants will possess the following skills / experience:
Hands on expertise in all aspects of design flows such as floor planning, placement optimization, clock tree synthesis, routing, crosstalk avoidance and physical verification
Excellent knowledge of place and route methodologies including implementation requirements for mixed-signal designs
Experience in leading block level and full chip timing closure & Physical Design activities.
Hands on-experience using low power methodologies (power gating, multi-Vt flow, power supply management etc.) and power analysis tools
Excellent understanding and hands on experience with timing constraints, advanced timing closure methodologies and ECO generation.
Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM, etc.)
Expertise in all areas of physical verification (DRC/LVS/ERC/ANT).
Experience with 65nm,55nm, 40nm and 28nm technologies from multiple foundries.
Proficiency in Tcl and Perl scripting.
Expertise in ICC/Innovus, PrimeTime, StarRC-XT, Formality, Calibre and Redhawk or equivalent.
Excellent written and verbal communication skills
Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals.
3-8 years experience in Physical Design
Masters / Bachelor’s Degree in Electrical / Electronics Engineering