Our client delivers value to its customer by focusing on providing R & D services in the space of Embedded Software, VLSI Design and System Design.
They are looking for Physical Design Engineer to be based at Bangalore with the following skills:
Total 3 to 8 years of experience in Implementation of multimillion gate SoC designs in cutting edge process technologies (28nm,16nm,14nm & below ).
Must have strong hands-on expertise on any of the aspects of physical design including Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM and DFY and Tapeout.
Must have expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep-sub micron processes required.
Must have understanding of process variation effects, and experience in variations analysis/modeling techniques and convergence mechanism.
Must have expertise in Synopsys IC compiler, Magma or Cadence SOC encounter physical design tools.
Must have experience in scripting using Tcl or Perl
Kindly send your profile in word document to tulsiarora(at)mysearch.in.net or call on 90361 39000