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MTS / SMTS / Principal ASIC Design Engineer

Keywords / Skills : RTL, Verilog, VHDL, SV, System Verilog, DSP, PCIE, Ethernet, Matlab, STA, Micro-Architecture, ASIC, SoC

4 - 14 years
Posted: 2018-12-07

Job Description
Location : Bangalore

Our client ( US Based MNC listed in New York Stock Exchange) is a leading developer, and global supplier of high-speed connectivity solutions for data centers, enterprise and WLAN applications. The transition to 10Gb Ethernet and Multi-Gig Ethernet is currently underway, driven by the consolidation of data in the cloud and the mobile revolution. Its 10GBASE-T and PHY product lines lead the market with low-power, high-performance, and high-density silicon solutions

Location : Bangalore

Principal Digital Design Engineers

Responsibilities:

§ Develop key blocks of logic in a next generation physical layer/mixed signal SOCs

§ Perform hardware feasibility analysis and come up with a micro-architecture specification helping it map to a high performance, implementable design

§ Work with verification, DFT, synthesis, circuits, backend implementation teams to realize quality implementation

Requirements:

§ Minimum BE/BS degree in Electrical/Electronics/Computer science required

§ At least 4-14 years of logic design and RTL coding experience with sound knowledge on verification and implementation concepts

§ Experience in physical layer ASIC architecture, micro-architecture development, design and debug

§ Ability to code readable, maintainable, verifiable and synthesizable logic in Verilog and/or SystemVerilog

§ Experience with lint, synthesis, CDC, STA, formality, ECO process, tool flows and scripting

§ Knowledge in one or more of the following areas, a definite plus

· Ethernet (layer 2/3/4 protocols, GMII/XGMII, integration of PHY layer)

DSP fundamentals/Filter/FFT design/Datapath design/Error Control Coding/PCIE/Ethernet
· Computer architecture/Processor fundamentals

*

Preferred Qualifications:

§ Strong knowledge of ASIC design methodologies and flows

§ Ability to proactively take on responsibilities and competent to work in a start-up environment

§ Worked with product development companies and having seen at least a couple of tape-outs

§ Experience with silicon bring-up in the lab and debugging is a definite plus

§ Experience with FPGA realizations of higher complexity designs

§ Ability to work with teams spread across geography with excellent communication skills

Contact:

Uday Bhaskar
Mulya Technologies
"Mining the Knowledge Community"
muday_bhaskar@ yahoo.com
Ref : RTL Design -DSP



About Company

Our client ( US Based MNC listed in New York Stock Exchange) is a leading developer, and global supplier of high-speed connectivity solutions for data centers, enterprise and WLAN applications. The transition to 10Gb Ethernet and Multi-Gig Ethernet is currently underway, driven by the consolidation of data in the cloud and the mobile revolution. Its 10GBASE-T and PHY product lines lead the market with low-power, high-performance, and high-density silicon solutions
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