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Memory Layout Engineers

Keywords / Skills : Memory layout design, memory integration, 16nm, 14nm, finfet, DRC , LVS, physical verification, IR / EM, bit cell, IO blocks

3 - 8 years
Posted: 2018-08-20

Software Engineer/ Programmer
B.E/B.Tech, M.E/M.Tech/MS
Posted On
20th Aug 2018
Job Description
Job Description:

Location: Bangalore, Noida

Experience: 3 to 8years

Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context.

Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies

Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space.

Good handle on IR/EM related issues in memory layouts.

Must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks.

Strong knowledge of ultra-deep sub-micron layout design related challenges and good understanding of DFM guidelines.

Experience & or strong interest in memory compilers developed.

Excellent and demonstrated team player with ability to work with external customers and in cross functional teams


Uday Bhaskar

Mulya Technologies

"Mining the Knowledge Community"


About Company

Our client is a preferred semiconductor design service partners to multiple Fortune 500 companies in the Automotive, Consumer Electronics, Industrial IoT and Medical electronics space. The company enables its customers achieve their time-to-market window by delivering first pass silicon designs and engage with product engineering teams across the globe to design SoC. HQ in, California, with multiple development and services centers in India, Canada and Germany
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