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Keywords / Skills : "Circuit Designers", "Memory Layout", "Leaf Cell / Block level Layouts", "Finfet", "Leafcell", DDR

3 - 7 years
Posted: 2019-04-03

Job Description
  • Independent work execution 
  • Experience working with circuit designers
  • Good experience in leaf cell/block level layouts
  • Good experience in memory compiler layouts
  • Good understanding and hands on experience using verification tools (Calibre) for LVS and DRC
  • Experience in handling IR/EM related issues in memory layouts.
  • Awareness of second order effects
  • Experience of working in 16nm / 14nm / 10nm/ 7nm/ Finfet technology node ispreferred 
  • Good communication skills and a team player

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