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Keywords / Skills : RTL, Verilog, EDA, ASIC, VLSI, FPGA, Timing

2 - 7 years
Posted: 2019-09-05

Job Description
a. Digital Logic Micro-architecture & Design, including multi-clock domains, power optimized designs, DFT
b. RTL Coding, preferably in Verilog
c. Strong understanding of timing, area optimizations
d. Ability to develop a micro-architecture, from a high-level architecture definition.
d. Work with Verification team - for functional and coverage closure
e. Work with Implementation team - for design closure for area/power
f. Expertise in different bus protocols - AXI, AHB etc, and Interface specifications - PCIE, DDR 

a. Experience with System Verilog

b. Strong background in computer architecture

c. Experience in algorithms

d. Good programming skills in C and scripting languages like Perl, Python
f. Drive for excellence, outstanding team player, Strong problem solving, analytical skills and debugging skills

g. Excellent verbal and writing skills

h. Good knowledge of standard EDA tools for FPGAs and ASICs

About Company

Smart IOPS ( is a Silicon Valley based corporation, founded in 2013, with most of the Research & Development happening at its research centers at Bangalore and Trivandrum. We have developed the fastest flash memory based Sold State Drive (SSD) in the world, as validated by independent bench marks ( The solutions are very well suited for use in High Performance Computing, Big Data Analytics, Databases, AI & ML , Content Delivery and for Enterprise Data
We continuously look for motivated and aspiring engineers with M.Tech/B.Tech in ECE & CS. Selected engineers will work with some of the best technologists in the industry, both in Indian and in Silicon Valley. SmartIOPS is an exciting place for young engineers who are eager to learn different aspects of electronic system design, as well as the industry domain of "Storage", which is an exciting field with huge growth potential.
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