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Keywords / Skills : Scan, ATPG, Coverage analysis, LBIST, BSCAN , MBIST, Full chip testability

5 - 15 years
Posted: 2019-02-11

Industry
Semiconductor
Function
IT
Role
Hardware Design Engineer
Hardware Design Technical Leader
Education
BE
BTech
Posted On
11th Feb 2019
Job Description
Role: DFT Engineer/Manager

Experience 5-15 years

Skills Scan, ATPG, Coverage analysis, LBIST, BSCAN (optional), MBIST (optional), Full chip testability and coverage



Description • Candidate must have handled scan insertion, pattern generation & simulations (timing sims), debug, handled different ATPG tools and flows, understand scan compression flows.

• Should understand controllability and observability concepts, should understand why DFT coverage is important and how to improve coverage.

• Ideal candidate should have done DFT architecture and planning for a full chip, by himself.

• Usage of functional test patterns to improve test coverage, analog blocks test exposure not necessary but good to have.

• Good to have shell scripting /Perl/Python/Tcl experience for productivity improvement.

• Good to understand boundary scan concepts and worked hands-on with JTAG tools. Should know 1149.1 and 1149.6 IEEE standards

• Good to have knowledge of reparable memories, MBIST algorithms. MBIST - controller generation, integration at block and top level, pattern gen & simulations.

• Good to have exposure to post silicon debug & industry level ATE exposure

• Cadence tools and flows - Genus, Modus - good to have


Please send your updated cv to jancyATpeopleplusindiaDOTcom to discuss.


About Company

PEOPLEplus Professional Services Pvt Ltd is a Bangalore based Staffing and HR & Operations Solutions Provider for domestic and international companies and an acknowledged leader, especially in the R&D and High Technology domains, supporting some of the world’s best companies in identifying some of the best talent in the industry.
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