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DFT Engineer - Bangalore and Onsite

Keywords / Skills : ASIC, System verilog, SOC, VLSI, Test cases, PCIE, IPS, Simulation, Email, Notes

10 - 15 years
Posted: 2019-01-14

Team Leader/ Technical Leader
Posted On
14th Jan 2019
Job Ref code
Job Description
Job Description:
    Functional Area : IT - Software Functional Role : IT Software - Embedded / EDA / VLSI / ASIC / Chip Des Experience : 4 - 8Years Job Location : Bangalore Job Description : Work Package Verification of the test logic , test pattern generation , test pattern re - simulation (unit delay and timing) for Synopsys IPs: DDR3 / 2 , PCIe , and USB2 / 3 within the SOC Use IP provided test cases and create new test cases. Deliver SOC level resimulated test pattern for ATE for the mentioned IPs. Here are the expertize required in the candidate Verification expert (Mostly Verilog , some System Verilog knowledge will be of advantage). Cadence NCSIM simulation tool. ATE pattern generation , re - simulation and pattern sign - off knowledge. Candidate will be using Lantiq test bench and will be introduced to TOPS Flow{internal tool} for test pattern generation and re - simulation. Experience: 4 to 8 years Location: Bangalore(Trip to Singapore)
Desired Candidate Profile
    Please refer to the Job description above

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