Scan insertion & ATPG using Fastscan/TestKompress /DFTCompiler/DFTMax/DFTAdvisor/TetraMax.
Pattern Simulation with and without timing annotation & debugging.
Must pattern Simulation with and without timing annotation & debugging simulation mismatches (VCS/Modelsim/NCSim).
Candidate should have knowledge of Debussy/Verdi.
Must have familiarity with WGL/TDL file formats.
Scan compression techniques/LogicBIST.
Should exposure to Memory BIST insertion tools (preferably LogicVision MBIST/Mentor MBISTArchitect).
Boundary Scan, JTAG concepts, Core testing using P1500.
Candidate must have basic understanding of Tester requirements, basics of synthesis and timing and must the knowledge of formal verification. Exposure to SoC level DFT.
-Candidate should have experience with Scan, ATPG and simulations with Synopsys and Mentor tools (DFT Compiler, Fastscan,).
-If candidate is having logic Bist knowledge that is a plus.
-Should have worked hands-on extensively on full chip DFT design, implementation, vector generation/verification, JTAG, Memory BIST and simulation.
-Candidate should have experience in DFT configuration mechanism, multiple clock domains, desired operational speeds, fault models etc.
Should have decent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA.
Candidate should be responsible for Diagnostic Tool generation for ATPG and MBIST and bring-up on ATE.
Must have developing, enhancing and maintaining scripts as necessary.
Should have experience in ASIC/DFT - simulation, Silicon validation.
Should have detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement.
Candidate should know in depth knowledge and hands on experience in ATPG - coverage analysis, Transition delay test coverage analysis.
In depth knowledge of Memory verification, repair and failure root-cause analysis.
Experience with any of these tools is required
ATPG - Tetramax, TestKompress
MBIST - Mentor ETVerify
Bachelor's Degree in Electrical Engineering, Computer Engineering or related field; MS or PhD preferred.
Must have good knowledge of scripting languages (Python, TCL or Perl) for automating solutions.
Deep understanding of Design for Test (DFT) structures is required.
Demonstrated experience in scan based testing, Scan Compression, Memory BIST.