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Keywords / Skills : ATPG, BIST, MBIST, Perl

4 - 8 years
Posted: 2019-06-08

Job Description
Mandatory Skills:

• Full-chip DFT leadership experience with multiple design Tape Outs

• Test architecture creation and drive the Complete full Chip DFT implementation & verification of complex ASICs

• Proven Experience in Stuck-At, TDF, MBIST, BSCAN/JTAG, IDDQ schemes & verifications.

• Chip-level & hierarchical Scan insertion with Compression Techniques (EDT/OPMISR+).

• Hands on Experience with Synopsys/Tessent/Candence DFT tools & flows

• Leading junior teams and Mentoring.

Good to Have:

• Exposure to LBIST & I-JTAG implementation & verification.

• Knowledge of cross functional domains (SYN, LEC, STA, PD)

• Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process

• Excellent Customer interaction, Communication and Team work skills


Key Skill(s)

About Company

STRESS Consulting
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