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Keywords / Skills : DFT, ATPG, BIST, MBIST

2 - 12 years
Posted: 2019-04-23

Industry
IT/Computers - Hardware
Function
IT
Role
Team Leader/ Technical Leader
Posted On
23rd Apr 2019
Job Description
Job description:

• Responsible for independent planning and execution of PNR for HM Design/Top level (Netlist-to-GDSII)

• Responsibility/ownership of block level physical implementation for production quality 40nm/28nm/20nm/14nm/7nm designs Required Skills:

• Must have participated in all stages of DFT activities • Experience on Chip-level DFT insertion with sound knowledge of Scan insertion, compression, MBIST & JTAG techniques

• Should have good post silicon DFT bringup and debug experience

• Create test plan for complex ASICs and drive the DFT implementation & verification

• TCL / Perl scripting and automation is a plus • Strong problem-solving skills and teamwork, self-motivated, excellent verbal and written communication.

• Hands on experience using Fastscan, Flextest and other multi-vendor DFT tools

• Good team player with excellent communication skills, interfacing with the architecture / design teams


Key Skill(s)

About Company

STRESS Consulting
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