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Design Verification Engineer

Keywords / Skills : SystemVerilog, HDL languages

3 - 10 years
Posted: 2019-04-13

Job Description
• Candidate will be responsible for developing verification plans and architecting test benches to validate DUT (Devise Under Test) functionality in simulation of application specific integrated circuit (ASIC/Integrated Circuit).

• Interpreting architectural and design requirements;

• Writing verification test plans and requirements;

• Developing and using complex test benches;

• Implementing directed and constrained random test cases;

• Collecting, analyzing, and enhancing functional and code coverage;

• Debugging issues in the requirements, tools, simulation environment, test cases, and DUT;

• Performing Object Oriented programming (System Verilog);

• Participating in System Verilog Verification using a framework such as UVM or other industry standard methodologies;

• Verification automation and scripting.

• Hardware/Firmware interaction and Firmware programming; and, knowledge of Microprocessors and assembly language.

Qualification- Proficient with SystemVerilog, HDL languages and Object Oriented Programming.

Education- BS or MS (Electrical or Computer Engineering ) or Equivalent Degree with 3 years of experience.

About Company

Marvell (MRVL) is a global leader in providing complete silicon solutions and Kinoma® software enabling the "Smart Life and Smart Lifestyle." From storage to cloud infrastructure, Networking and connectivity. Marvell's diverse product portfolio aligns complete platform designs with industry-leading performance, security, reliability and efficiency. At the core of the world's most powerful consumer, network and enterprise systems, Marvell empowers partners and their customers to always stand at the forefront of innovation, performance and mass appeal. By providing people around the world with mobility and ease of access to services adding value to their social, personal and work lives, Marvell is committed to enhancing the human experience.

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