Neugene International Solutions
Keyskills: Design, ASIC, SOC, EDA, Vlsi Design...RTL, RTL Design, Verilog, SOC
Summary: JD for RTL Verification:
No Of positions:- 25
Exp :- 2-5 yrs
Engineering process and methodologies. Exposure to the complete lifecycle of ASIC Flow is essential. I..
Bengaluru / Bangalore, Mumbai