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  • Mulya Consulting
    Keyskills: Physical Design, Floor planning, Place & route, DRC, STA, Timing Closure, Timing Analysis, ECO, CTS, power planning, LVS, Netlist, floorplanning, power planning, GDSII, EDA, routing, IR drop, IP hardening, CPF, UPF
    Summary: Director Physical Design - Bangalore
    Bengaluru / Bangalore
    13-20 years
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    Posted : 25th Jun 2018
  • Mulya Consulting
    Keyskills: soc verification system verilog uvm gls ethernet sv dv ip verification specman ovm pci pcie amba ahb axi codecs sas scsi iscsi dma
    Summary: Looking for 3 to 8years of experience in IP Verification This role will include- BuildSV, SV UVM, OVM based environments. Build Specman eRM Based Environments
    Bengaluru / Bangalore
    3-8 years
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    Posted : 25th Jun 2018
  • Mulya Consulting
    Keyskills: IO Circuit Design, Spectre, Spice, 16nm, 14nm, SAR, DDR, DDR2, DDR3, DDR4, DDR5, SDIO, IO, ESD
    Summary: Hands on experience on IO Circuit Design , DDR2,DDR3 , I2C , SDIO Exposure to FinFet based designs Exposure to Overvoltage design,ESD and Reliability,aging Ability to Review Layout ..
    Bengaluru / Bangalore
    2-7 years
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    Posted : 25th Jun 2018
  • Mulya Consulting
    Keyskills: Digital Design, Front-end Design, Front end Verification, ASIC, Verilog, Systemverilog, SOC, VCS, VHDL, NCSIM, ModelSIM, Synthesis, Physical Design, Timing closure
    Summary: Digital Front End Design & Verification Sr Engineers/ Leads for Ahmedabad locations with 3 - 7 years of experience.Experience in ASIC or SoC design flow. FE Methodologies , UVM / Flow including sy..
    Ahmedabad
    3-8 years
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    Posted : 25th Jun 2018
  • Mulya Consulting
    Keyskills: Analog, Circuit Deisgn, finfet, 16nm, 14nm, Low noise, Large die, Cadence virtuoso, Cadence Spectre, ADC, DAC, INA, image sensors,
    Summary: Looking for Analog circuit Design Engineers for Ahmedabad locations with 2 - 5 years of experience.
    Ahmedabad
    2-6 years
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    Posted : 25th Jun 2018
  • Mulya Consulting
    Keyskills: Analog circuit design, finfet, 16nm, Low Noise, Large Die, Cadence Virtuoso, Cadence Spectre, ADC, DAC, Image sencors
    Summary: Design of various low noise circuits like Bias blocks, Low noise amplifiers, Column ADCs (single/dual slop).
    Hyderabad / Secunderabad
    2-7 years
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    Posted : 25th Jun 2018
  • Mulya Consulting
    Keyskills: FPGA, EDA, VHDL, RTL, Verilog, Verification, PCIE, PCI, Ethernet, Serdes, PHY, Xilinx, Quartus, Logic Analyzer
    Summary: Client: US Based MNC Our client seeks FPGA designers, verification engrs, technical lead and team manager with excellent technical skills to deliver cutting edge FPGA solutions. This role is ..
    Delhi, Gurgaon
    5-15 years
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    Posted : 25th Jun 2018
  • Mulya Consulting
    Keyskills: FPGA, UVM, Altera, Xilinx, System Verilog, SV, System C, PCIE, PHY, Serdes, Ethernet,
    Summary: Client: US Based MNC Our client seeks FPGA designers, verification engrs, technical lead and team manager with excellent technical skills to deliver cutting edge FPGA solutions. This role is ..
    Delhi, Gurgaon
    5-15 years
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    Posted : 25th Jun 2018
  • Mulya Consulting
    Keyskills: RTL, Verilog, SOC, ASIC, VHDL, Front End Design, FPGA, Linting, CDC, STA
    Summary: Our client is a preferred semiconductor design service partners to multiple Fortune 500 companies in the Automotive, Consumer Electronics,RTL Design practice is responsible for that part of the AS..
    Ahmedabad, Bengaluru / Bangalore
    3-11 years
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    Posted : 25th Jun 2018
  • Mulya Consulting
    Keyskills: UVM, SystemVerilog, SV, SoC, IP, GLS, PCIe, Ethernet, USB, MIPI, DDR
    Summary: Our client is a preferred semiconductor design service partners to multiple Fortune 500 companies in the Automotive, Consumer Electronics,.Digital Verification team is working on IP verification a..
    Ahmedabad, Bengaluru / Bangalore
    3-11 years
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    Posted : 25th Jun 2018
  • Mulya Consulting
    Keyskills: PCI, PCIE, RTL, Verilog, System Verilog, SV, Lint, CDC, DFT, LEC, UPF, DMA, PHY, Serdes, ASIC, SoC, micro-architecture
    Summary: Our client ( US Based MNC listed in New York Stock Exchange) is a leading developer, and global supplier of high-speed connectivity solutions for data centers.Extensive experience in integration a..
    Bengaluru / Bangalore
    4-14 years
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    Posted : 25th Jun 2018
  • Mulya Consulting
    Keyskills: MAC, PTP, PCS, System Verilog, SV, Lint, CDC, DFT, LEC, UPF, ASIC, SoC, micro-architecture
    Summary: Our client ( US Based MNC listed in New York Stock Exchange) is a leading developer, and global supplier of high-speed connectivity solutions for data centers.RTL Design and implementation of MAC/..
    Bengaluru / Bangalore
    4-14 years
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    Posted : 25th Jun 2018
  • Mulya Consulting
    Keyskills: RTL, Verilog, VHDL, SV, System Verilog, DSP, PCIE, Ethernet, Matlab, STA, Micro-Architecture, ASIC, SoC
    Summary: Our client ( US Based MNC listed in New York Stock Exchange) is a leading developer, and global supplier of high-speed connectivity solutions for data centers.DSP fundamentals/Filter/FFT design/Da..
    Bengaluru / Bangalore
    4-14 years
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    Posted : 25th Jun 2018
  • Mulya Consulting
    Keyskills: MIPI, CSI, DSI, CPHY, DPHY, RTL, Verilog, ASIC, SOC, VHDL, Front End Design, Lint, CDC, DFT, LEC, UPF, Serdes
    Summary: Our client ( US Based MNC listed in New York Stock Exchange) is a leading developer, and global supplier of high-speed connectivity solutions for data centers.experience in integration and validat..
    Bengaluru / Bangalore
    4-14 years
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    Posted : 25th Jun 2018
  • Mulya Consulting
    Keyskills: RTL, Verilog, ASIC, SOC, VHDL, Front End Design, Lint, CDC, DFT, LEC, UPF, MACSEC, IPSec, AES, SHA, RSA
    Summary: Our client ( US Based MNC listed in New York Stock Exchange) is a leading developer, and global supplier of high-speed connectivity solutions for data centers.- Extensive experience with MACSEC/IP..
    Bengaluru / Bangalore
    4-14 years
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    Posted : 25th Jun 2018
  • Mulya Consulting
    Keyskills: Memory layout design, memory integration, 16nm, 14nm, finfet, DRC , LVS, physical verification, IR / EM, bit cell, IO blocks
    Summary: Looking for 3 to 8years of experience in layouts of memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Experience in 16nm / 14n..
    Bengaluru / Bangalore, Noida
    3-8 years
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    Posted : 19th Jun 2018
  • Mulya Consulting
    Keyskills: memory design, SRAM, DRAM, Memory Characterization, Custon Circuit, compiler automation, Critical Path Modelling
    Summary: Looking for 2 to 7years of experience in Memory Circuit Design and Characterization
    Bengaluru / Bangalore
    2-7 years
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    Posted : 19th Jun 2018
  • Mulya Consulting
    Keyskills: memory design, Memory modelling, SRAM, TCAM, Verilog models, FE, Memory Verification, Model quality Check
    Summary: Memory FE/Verilog models development & verification.
    Bengaluru / Bangalore
    2-7 years
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    Posted : 19th Jun 2018
  • Mulya Consulting
    Keyskills: System Verilog UVM SOC Verification OVM VMM PCIE Design Verification USB Embedded Systems Chip Design SATA Ethernet
    Summary: Looking for 3 to 8years of Experience in SOC Verification at least one protocol of SATA, USB, Ethernet, PCIE and at least one methodology, OVM, UVM, VMM or RVM.
    Bengaluru / Bangalore
    3-8 years
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    Posted : 18th Jun 2018
  • Mulya Consulting
    Keyskills: System Verilog, UVM , SOC Verification, OVM , VMM , PCIE, Design Verification , USB, Chip Design, SATA, Ethernet
    Summary: Looking for 3 to 8years of experience in SOC Verification, Systeme Verilog and at least one protocol of SATA, USB, Ethernet, PCIE Expert at Verification - Coverage Driven Test Planning, Architec..
    Bengaluru / Bangalore
    3-8 years
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    Posted : 18th Jun 2018
  • Mulya Consulting
    Keyskills: IO Layout, GPIO, EM-IR, LU rules , EM –IR & parasitic aware routing, CMOS Fundamentals, IC-Fabrication & Circuit-basics
    Summary: Looking for experience in layout-design of GPIO & other High-Speed IO’s in cutting-edge technologies. Job Location: Bangalore, Hubli, Kolkata
    Bengaluru / Bangalore, Kolkata
    3-6 years
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    Posted : 4th Jun 2018
  • Mulya Consulting
    Keyskills: CAD, signal integrity, timing flows, circuit design , Synopsys, Cadence, Mentor, Ansys, static timing analysis, cell characterization, design checks, electro-migration, LVS, EMIR
    Summary: CAD engineers : Semiconductor Domain
    Hyderabad / Secunderabad
    3-8 years
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    Posted : 21st May 2018
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