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STA Tools (Primetime) and Flow, ASIC Timing constraints generation, Pune/Hyderabad/Bangalore.

Keywords / Skills : STA, ASIC Timing Constraints generation and timing Closure.

3 - 13 years
Posted: 2018-02-28

Nationality
India
Industry
IT/ Computers - Hardware
Function
IT
Role
Hardware Design Engineer
Hardware Design Technical Leader
Posted On
28th Feb 2018
Job Description
Please find below the company profile and technical requirements for this role.

In case you are interested, Please revert with your updated resume, with the following details mention below. Please share if you have some references for the same.

Total & relevant exp :-

Expertise in STA Tools

• At least 5+ years’ experience in ASIC timing constraints generation and timing closure.

• Expertise in STA tools (Primetime) and flow.

• Knowledge of timing corners/modes, process variations and signal integrity related issues.

• Hands on experience in timing/SDC constraints generation and management.

• Proficient in scripting languages (Tcl and Perl).

• Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools.

• Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups. Self-starter and highly motivated.

• Should be an expert in chip / block level STA

• Perl/tcl experience to parse reports/logs and highlight issues

STA / Synthesis experience in Synopsys/Cadence tool flows.

2. Current location:

3. Current CTC:

4. Expected CTC :

5. Joining Period :(Buyout option or Nego.)

6. Reason for a job change:

7. Ready to Relocate?(If Yes, Why):

8. Do you have Passport(Valid) : ?

9. Home town :

Warm Greetings!!!

I represent Ascentt where we offer an end-to-end service portfolio of IT strategy and implementation services, enabling us to become an exclusive partner with our clients and helping them on all aspects of their Information Technology Initiatives. We provide clients with a full spectrum of project life-cycle management and post production support, relating to their IT needs including: IT strategy and Implementation Road map, Business Process Analysis, Requirements Gathering, Application Design, Architecture and Infrastructure Sizing and Assessment, Application Development, Performance Tuning, Testing and QA, and Deployment and Production Support. Ascent Cyber Solution's ability to provide Services through the entire project life cycle means our clients can have one consistent implementation partner to deliver each phase of their project. (http://www.ascentt.com/)

Project Partner: CMMI Level 3 Company.

Bullet Points :

Founded 1991

Headquarters- Hyderbad, Andhra Pradesh.

Employees 14000 + across the globe.

Our Company provides engineering, manufacturing, geospatial, network and operations management services to global industry leaders. We leverage the power of digital technology and advanced analytics capabilities, along with our domain knowledge and technical expertise, to help our clients solve complex business problems. As a Design-Build-Maintain partner that takes solution ownership across the value chain, we empower our clients to focus on their core, innovate, and stay ahead of the curve. Relationships lie at the heart of how we work. We partner with organizations in ways that best suit their culture and requirements. With nearly 14,000 employees in 21 countries, we combine global delivery with proximity to our clients, functioning as their extended team. Our industry focus spans aerospace and defense, medical, telecommunications, rail transportation, semiconductor, utilities, industrial, energy and natural resources.

Job Description-

STA : Senior Engineer / Technical Lead / Architects.

Experience: 4 to 14 years

Location: Hyderabad / Bangalore / Pune

Job Description:

• At least 5+ years’ experience in ASIC timing constraints generation and timing closure.

• Expertise in STA tools (Primetime) and flow.

• Knowledge of timing corners/modes, process variations and signal integrity related issues.

• Hands on experience in timing/SDC constraints generation and management.

• Proficient in scripting languages (Tcl and Perl).

• Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools.

• Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups. Self-starter and highly motivated.

Roles & Responsibilities: •

• Create/update timing constraints chip level timing constraints

• Should be able to run synthesis analyze timing violations

• Debug the issues – identify design and constraint issues

• Make edits timing constraints •Create TCL automation scripts for DC/PT tools using attributes

Required Skills:

• Should be an expert in chip / block level STA

• Perl/tcl experience to parse reports/logs and highlight issues

STA / Synthesis experience in Synopsys/Cadence tool flows.

Early response will be highly appreciated.



About Company

Our Company provides engineering, manufacturing, geospatial, network and operations management services to global industry leaders. We leverage the power of digital technology and advanced analytics capabilities, along with our domain knowledge and technical expertise, to help our clients solve complex business problems. As a Design-Build-Maintain partner that takes solution ownership across the value chain, we empower our clients to focus on their core, innovate, and stay ahead of the curve. Relationships lie at the heart of how we work. We partner with organizations in ways that best suit their culture and requirements. With nearly 14,000 employees in 21 countries, we combine global delivery with proximity to our clients, functioning as their extended team. Our industry focus spans aerospace and defense, medical, telecommunications, rail transportation, semiconductor, utilities, industrial, energy and natural resources.
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