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STA - Functional Lead

Keywords / Skills : STA, "Static Timing Analysis", SSTA, "physical Design", DFT, PrimeTime, "Prime Time", Tempus, PT, PTSI, Synthesis, RC, DC, "RTL Compiler", "DC Compiler", ATE, RMP, "Timing Closure", signoff, constraints

10 - 15 years
Posted: 15th Aug 2017

Job Description
FUNCTIONAL LEAD - STA

Location: Bangalore, India.
Minimum Educational Qualifications: B.Tech/Masters degree in electronics
Relevant Experience: 11 - 15 years
No of Opening: 1
Job Description: Complete understanding of Syn/STA concepts (Synthesis, Timing, Equivalence Checks, Extraction, Noise, Power, UPF/CPF) and various flow
Develop/Plan complete DFT/test strategy for the device as per SOW
Create DFT implementation plan, delegate to team members and tracking
Test mode timing support/debug and closure at full chip level
Handle post-silicon pattern generation, Validation and ATE debug/support
Understanding Test/DFT modes SDC
Complete familiarity of tools used in DFT implementation (DC/RC, Tk/Tmax, Virage/Mentor memory BIST, Mentor Bscan) with expertise in one of them
Independently handle IP verification strategy and implement and verify the same
Good exposure to STA tool. Assist STA team in timing closure for DFT modes
Good scripting skills (TCL/Perl)
Familiarity with PD concepts/flow and assist PD team if and when required
Own full chip responsibilities
Interact with DM/FM, STA/PD/test/qual team to communicate work progress and closure
Interact with tool vendors and debug tool related or IP related issues independently
Have foresight into execution. Create risk mitigation plan (RMP)
Participate in different project reviews. Conduct team meeting regularly
Generate/collect feedback from team members on project/tasks flow and initiate correction/improvement in methodology
Participate in Focal process

Contact:
Uday
Mulya Technologies
"Mining the knowledge Community"
Email: muday_bhaskar@ yahoo.com
Desired Skills and Experience
STA, "Static Timing Analysis", SSTA, "physical Design", DFT, PrimeTime, "Prime Time", Tempus, PT, PTSI, Synthesis, RC, DC, "RTL Compiler", "DC Compiler", ATE, RMP, "Timing Closure", signoff, constraints


About Company

Our Client applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing, and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300 designs and shipped over 110 million ASICs to date. Privately-held, they employ over 250 people in Silicon Valley and around the world
Advantages:
Work on cutting-edge process nodes - 28, 16/14 downto 7nm
Implement next gen technologies like 2.5D ASICs, Ultra low-power IoT, Interlaken & HBM, Multi-CPU subsystems, etc.
Get Block and Top level ownership in design and silicon
Interact with Global Customers on system and chip level details
Enjoy a friendly and learning-supported employee-first environment
Benefit from adequate benefits which make our client a healthy, happy work place
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