BS / MS in EE/CSE from a reputed University.
Good knowledge of EDA tools from Synopsys, Cadence and Mentor required. In particular experience with PTSI, First Encounter, Nanoroute, Calibre, StarRC, and Conformal is essential.
Good knowledge of VLSI process and device characteristics, to make optimal trade-off between performance and power.
Good knowledge of standard cell libraries circuit design and cell layout.
Good understanding of static timing analysis (STA), EM/IR and sign-off flows.
Strong hands-on experience with:
Low power design techniques.
Floor planning, place & route, power and clock distribution, pin placement and timing constraints generation.
Timing convergence using high speed design techniques with signal integrity & EM/IR.
Physical design verification.
Functional verification at various levels of design hierarchy with respect to golden RTL by formal methods.
Prior experience with 16nm or finer geometries is a plus.
Good software and scripting skills (perl, python, tcl).
Self-driven individual and an excellent team player experienced in working with remote teams.
Must have good communication skills and the ability and desire to work as a team.
Candidate is expected to work on RTL to GDS for processor core designs, optimizing the implementations for power, timing and area.
To be responsible for and own all aspects of physical design and physical verification effort at a block level. Will also need to help out at the top level.
Develop, support and maintain physical design flows and methodologies.
Work closely with the design team to accomplish the objectives.
Responsibilities will include block level ownership of design, unit level verification, design reviews.
Work with multiple sites in a team environment particularly with offices in the US.
Expert in physical design of high frequency chips with emphasis on successful timing closure.