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Physical Design - Leads

Keywords / Skills : "Floor planning", CTS, , DRC, LVS, TCL, STA, DFT, ICC, "first Encounter", "SoC Encounter, Synthesis, DC, RC, ICC2, Innovus

6 - 13 years
Posted: 2017-11-05

Job Description
Leads- Physical Design
Location : Bangalore
No of Positions : 3
Experience : 6-13 years

Own project specific flow setup and maintenance.
Physical design tasks include floor-planning, place and route, CTS, timing closure, IR analysis and LEC for block level, full chip flat and hierarchical designs. Co-ordinate the full chip physical design and verification activities.
Physical design verification tasks include creating setup and scripts for DRC, LVS, Antenna and density checks, report generation, analysis, debug and implementing the fixes in the physical design database. This also includes DFM checks for the advanced node designs.
Ensure correct IP and pad-ring integration in block and flat designs.
Prepare training plan and conduct training of new PD/PDV team members, new tools flow set-up and any tool evaluations.
Work on IDP of the team members, performance management, etc. Responsible for the technical issues in projects running with the team members and guide them to resolve the issues.
Flag PD/PDV flow related issues to relevant person.
Ensure Check list items are followed / Verified within projects.
Take measures which saves time in future projects.( action items in flow revision)
Participate in Focal process

Contact:
Uday
Mulya Technologies
"Mining the knowledge Community"
Email: muday_bhaskar@ yahoo.com
Desired Skills and Experience
Physical Design Physical Verification Static Timing Analysis Timing Closure Floorplanning Clock Tree Synthesis Application-Specific Integrated Circuits (ASIC) Design Rule Checking (DRC) Layout Versus Schematic (LVS) TCL Very-Large-Scale Integration (VLSI) System on a Chip (SoC) STA, DFT, ICC, "first Encounter", "SoC Encounter"


About Company

US Based MNC
Company :Our Client applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing, and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300 designs and shipped over 110 million ASICs to date. Privately-held, they employ over 250 people in Silicon Valley and around the worldAdvantages:Work on cutting-edge process nodes - 28, 16/14 downto 7nmImplement next gen technologies like 2.5D ASICs, Ultra low-power IoT, Interlaken & HBM, Multi-CPU subsystems, etc.Get Block and Top level ownership in design and siliconInteract with Global Customers on system and chip level detailsEnjoy a friendly and learning-supported employee-first environmentBenefit from adequate benefits which make our client a healthy, happy work place
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