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Physical Design - Engineer / Sr. Engineer / Lead for Bangalore & Ahmedabad

E Infochips Limited
Keywords / Skills : sta, Static Timing Analysis, Timing Closure, Synthesis, Floorplanning, nm, physical design, Backend design, Place & route, Floor planning, DFT, LVS, DRC
Posted: 28th Mar 2017

Industry
Semiconductor
Function
IT
Role
Software Engineer/ Programmer
Team Leader/ Technical Leader
Posted On
28th Mar 2017
Job Description
Engineer would be responsible for doing physical design implementation; timing closure and Physical verification at block level.

He/She should execute block level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks, IR Drop, STA, Power and noise analysis.

Experience in Physical Design Implementation on advanced technology nodes like 28nm, 20nm, 16nm for block level implementation.

Good communication skills are a MUST.

Future onsite assignment (USA) opportunities.

About Company
eInfochips is a global product innovation partner recognized for technology leadership by Gartner, Frost & Sullivan, NASSCOM and Zinnov. eInfochips has contributed to 500+ products for top global companies, with more than 10 million deployments across the world.
The company is debt-free and profitable since inception in 1994.
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