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Physical Design Engineer / 2 - 5 Years / Hyderabad,Bangalore

Keywords / Skills : ASIC, Floor planning, P&R, Extraction, IR Drop Analysis, ICC, PT, PTSI, TEMPUS, DC, RC, VOLTA

2 - 5 years
Posted: 2018-01-09

Industry
Semiconductor
Function
Manufacturing/ Engineering/ R&D
Role
Design Manager/ Engineer
Posted On
9th Jan 2018
Job Description
Candidate must have strong back ground of ASIC Physical Design: Floor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.

Have some experience on advance Technology: 28nm, 40nm, 45nm, 65nm.

Hands on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS).

Candidate must independent planning and execute.

Must fully exposure to all aspects of design flows like floor planning, placement, CTS, routing, crosstalk avoidance, physical verification.

Candidate should have good exposure to high frequency design convergence and exposure to physical design methodology.

Must have ability to collaborate and resolve issues constraints validation, verification, STA, Physical design, etc.

Must have knowledge of low power flow (power gating, multi-VT flow, power supply management etc.).

Should circuit level comprehension of time critical paths in the design. Tcl or Perl scripting.

Candidate must have ability to handle technical deliveries with a small team of engineers.

Should be well versed with the level timing closure (STA), timing closure methodologies, ECO generation and predictable convergence.

Well versed with parasitic extraction, LVS or DRC and other Physical verification checks.

Candidate should be able to provide clear directions to the team in PNR issues.

Should have knowledge of clock tree synthesis, low power techniques, Timing analysis.

Good understanding of physical design flows, flow automation and design data management.

Desired Candidate


Candidate should have knowledge on ICC, Primetime, Synopsys tool set, Compiler.

Should have hands on experience on DRC & LVS, Floorplanning, placement, CTS, P&R.

Must have knowledge on block level timing closure activities.

Should develop new scripts or flows to improve the timing closure process.

Must understanding of PD flow and methodologies - primarily on block level place and route flow.

Candidate should ensure correct IP and pad-ring integration in block and flat designs.

Must take measures which saves time in future projects.

Candidate should have experience in backend flow including physical design, timing analysis to final tape out in 28nm and below. Hands on experience in standard backend tool flows is a must.

Participate in Focal process.

Candidate must have excellent communication skills.

About Company

Morgenall Management Consultant Pvt Ltd
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