Location : Bangalore
Digital Design Verification Engineer (1 Position)
10+ years of DV experience in building and architecting verification environments, preferably from scratch for multiple projects.
The engineer should have experience in writing testplan, creating & enhancing verification environments and be comfortable coding any portion of a test bench (models, checkers, scoreboards, coverage monitors, etc.).
Candidate should have experience in the development of constraint random DV environments for large ASIC blocks.
Languages: Must have experience in Verilog/SystemVerilog.
Methodology: UVM (must) and Specman (is a plus).
Experience with gate level simulation and debug is a plus.
Scripting: Perl, Python.
Experience with PCIe and/or networking (Ethernet) protocol is a must.
Experience with SoC verification is a plus.
Good interpersonal/communication skill.
Experience in emulation/hardware acceleration platforms is a plus.
Leading/Mentoring junior engineers.
Education and Experience:
BE, B.Tech (MS preferred) in Electrical Engineering, Computer Science, or related field
Minimum 8-10 years applicable experience.
"Mining the knowledge Community"
Email: muday_bhaskar@ yahoo.com